(1) Field of the Invention
This invention generally relates to semiconductor integrated circuits (ICs). In particular, it relates to a chip recovery circuit which is formed on an integrated circuit chip or on a semiconductor wafer provided with a plurality of functionally equivalent circuit blocks. The recovery circuit makes chip recovery possible by deactivating any circuit block in which abnormal operating characteristics are detected. The remaining circuit blocks may then be used.
(2) Description of the Prior Art
In order to deal with defective memory cells in a memory cell array, the redundancy technique has been used in the semiconductor field. In this technique, the memory is provided with spare memory cells which may be used in place of defective cells. In a memory array, spare rows and columns may be provided to replace defective rows and columns. However, the inclusion of additional cells increases production costs. It is also difficult to exchange these spare cells for the defective cells. Extra controls must be provided to effect such exchanges and this complicates the overall circuitry.
Logic ICs and similar devices are often provided with several circuit blocks which are functionally equivalent and virtually independent of one another. Types of circuit blocks may include shift registers, memory cell arrays, or gate arrays. Usually a power line, a ground line, and several input/output signal lines are coupled to each circuit block. in an integrated circuit of this type, an improperly functioning circuit block should not be used or should not be selected during use. However, in the prior art integrated circuit shown in FIG. 1, the power lines and ground lines of the circuit blocks 8.sub.1 to 8.sub.n are coupled to main power line 81 and main ground line 82 on the chip. If a power current abnormality occurs in even a single circuit block, the current becomes abnormal throughout the whole chip. Thus, the remaining circuit blocks may not used, even though they may be operating normally. One remedy is to isolate the faulty block from main line 81 or 82. However, problems arise in attempting to disconnect the power line, which is usually relative wide. If, as shown in FIG. 2, a main power line 91, consisting of a metal wire, and a power line 92, consisting of a metal wire in the circuit block, are separated by a gap of about 10 microns, a polysilicon film 93 may be used to make the connection between wires 91 and 92. Such a film must be relatively wide (up to 100 microns) in order to make the coupling resistance between wires 91 and 92 no greater than several ohms. One method of cutting polysilicon film 93 to disconnect the power line would be to directly irradiate it with a scanning laser beam. But because of the film's width, such a process would take a relatively long time and greatly reduce the production rate. In addition, a considerable amount of heat would be generated and could damage both the semiconductor substrate and main power line 91, further impairing reliability. These problems prevent the use of laser beam irradiation to cut such a film. In addition, it is extremely difficult to identify a block with abnormal operating characteristics. The identification is relatively simple if the current abnormality occurs for the first time at the onset of a specific operating mode, i.e. during selection of a particular circuit block. But if the abnormality occurs during all operating modes, such identification is not possible. As a result, chip recovery is impossible.